1. Field of the Invention
The present invention relates to solid state devices of the type employing a large number of semiconductor devices on an integrated circuit chip. More particularly, the present invention relates to input/output buffer circuits for such integrated circuit chips.
2. Description of The Prior Art and Related Information
Electro-Static Discharge (ESD) is an increasingly significant problem in integrated circuit design. Such potentially destructive electrostatic pulses are due to various transient sources such as human or machine handling of the integrated circuit chip during processing, assembly and installation of the chip. Such ESD events will typically originate at one or more of the integrated circuit electrical contact pads with the specific discharge path varying with the integrated circuit design and the size and polarity of the electrostatic charge applied to the pad. Increased device packing densities and diminished device geometries in modern VLSI chips have generally increased the susceptibility to damage from ESD pulses.
Having effective on-chip protection against ESD is very important because elaborate and expensive environmental controls can then be avoided when the integrated circuit is being handled by human operators and assembly machines. Also, for applications where the chip is unavoidably positioned adjacent sources of electrostatic buildup or high voltage rails such on-chip protection is the only type of protection against ESD available. Since the first circuitry electrically connected to the integrated circuit pads is normally some type of input/output buffer circuit, it is such circuitry which must bear the brunt of the ESD problem. Such input/output buffer circuitry serves to buffer the logic devices on the integrated circuit, which typically operate at relatively low voltage and current levels, from the voltage and current levels on the input/output pad which interfaces with external devices. In the case of a typical CMOS (Complimentary Metal Oxide Semiconductor) integrated circuit design, the CMOS devices in the integrated circuit will typically be buffered from the input/output pads by one or more CMOS inverters having wide Field Effect Transistors (FETs) which serve to buffer the internal logic gates from the input/output pad. Therefore, in a typical ESD event, a high voltage applied to an input/output pad would result in a high discharge current to flow through one of the legs of the CMOS inverter gate to V.sub.dd or V.sub.ss, respectively. One type of discharge path may occur from the output pad through the n channel FET through to V.sub.ss. Depending upon the polarity of the ESD voltage pulse supplied to the pad, the discharge may either proceed via an avalanche breakdown of the drain/channel junction of the n channel FET or via a forward biasing of the drain/channel diode. The avalanche breakdown type of discharge path is the most destructive since it is most likely to result in irreversible damage to the structure of the n channel FET.
In FIG. 1, a prior art approach to protection of an integrated circuit from ESD events is illustrated schematically for a simple CMOS inverter buffer circuit coupled to an integrated circuit output pad. As shown in FIG. 1, a diffusion resistor is positioned in series with the output pad and the buffer inverter. Such diffusion resistor will typically be an n or p type diffusion into the substrate of the integrated circuit having a sufficiently high resistance value such that upon occurrence of an ESD event, the discharge current through the p FET or n FET of the inverter will be reduced to an acceptable value. Since the resistor is formed as a diffusion into the substrate, the diffusion resistor also provides an alternate current path for the discharge current into the substrate, which is typically coupled to V.sub.ss. For this reason, the diffusion resistor is also schematically indicated with a diode symbol in FIG. 1 to illustrate the diode type contact between the diffusion and the substrate which provides this alternate current path.
Various modifications to integrated circuit designs, in addition to packing density, have increased the susceptibility of modern VLSI integrated circuits to ESD damage. One of many desirable characteristics of a CMOS integrated circuit is the ability to conduct a large amount of current. In order to achieve this design goal, the physical structure of a CMOS integrated circuit must undergo various modifications. Two of the most useful have been a reduction in the thickness of the gate oxide underneath the gate electrode, and a reduction in the gate length dimension. Since the current conduction capability of a CMOS integrated circuit device is inversely proportional to both gate oxide thickness and the physical gate length, to the first order, reducing these dimensions has been the design modification of choice in the semiconductor industry. For example, current CMOS integrated circuits have gate oxides which may be on the order of 200 .ANG. or less in thickness. This is in contrast to earlier designs where gate oxide thicknesses of 1,000 .ANG. were typical. Since the breakdown voltage of the gate oxide is proportional to its thickness, increasing at approximately one volt per 10 .ANG. of gate oxide, it will be appreciated that modern CMOS gate oxides are subject to breakdown at significantly lower voltages than earlier ICs, for example, 20 volts or less. Thus, shorting of the buffer FETs through degradation of the gate oxide during an ESD event may occur at relatively low voltages. The damage caused by this type of ESD discharge is often quite serious since the gate oxide will generally be permanently degraded by such ESD breakdown of the oxide.
The reduced physical dimensions in an active transistor, also give rise to a phenomenon known as "hot electron" injection; where high electric fields promote the dissociation of electron/hole pairs and the tunneling of energetic electrons into the gate oxide. The presence of these electrons in the gate oxide creates a fixed charge which further modifies the electric field in the channel region of the CMOS device, resulting in a higher conductivity at a given stimulus on the gate electrode. This change in the conductivity parameter is cumulative and can result in unreliable device parameters. This "hot electron" injection mechanism is also inversely proportional to the thickness of the oxide underneath the gate electrode and the length of the conductive channel underneath the gate electrode. Subsequent events will tend to follow the same discharge path through the weakened gate oxide and such current "lock-on" onto the weakened gate oxide will ultimately destroy the buffer FET. Gate oxides weakened by a reverse bias breakdown stress are especially susceptible to hot carrier injection at the point of weakness. Hot carrier injection is able to induce a weakness in the gate oxide by itself, through joule heating of the oxide by the increased current flowing in the channel area directly underneath the oxide. Weakening of the oxide, allowing enhanced hot carrier injection, resulting in increased current flow below the point of weakness, further weakening the oxide, results in ever increasing current in a run-away effect, which eventually destroys the device. See, for example, I.C. Chen, et al., The Effective Channel Hot Carrier Stressing on Gate Oxide Integrity in MOS FET, Proc. Int'l Reliability Physics Symposium, 1988; N. Khurana, et al., ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms, Proc. Int'l Reliability Physics Symposium, 1985. Various other factors have also contributed to the increased susceptibility of modern VLSI integrated circuits and in particular CMOS integrated circuits to ESD damage. See, for example, C. Duvvury, et al., ESD Protection Reliability in One Micron CMOS Technologies, Proc. Int'l Reliability Physics Symposium, 1986. The aforementioned problems resulting from reduced device dimensions become particularly significant for gate oxide thicknesses less than approximately 275 .ANG. and channel lengths less than approximately 2 microns. Further increases in CMOS integrated circuit performance, i.e., increased current drive capability, through reduction of the gate oxide thickness and reduction of the gate length dimension, will result in increased susceptibility to the problems of low breakdown voltages and hot carrier injection. These problems must be solved before further advances in increasing device performance through reducing device dimensions may be practically accomplished.
The most common approach to overcoming the aforementioned problems in protecting modern VLSI integrated circuits against ESD damage has been to increase the resistance of the resistor placed in series between the pad and the buffer circuit. Since this increases the load driven by the buffer circuit, however, this approach will be unacceptable for a great many applications. For example, in an output buffer circuit required to drive a relatively high current load through the output pad, such a high resistor in series with the output pad will be unacceptable. Various other applications, such as applications requiring fast response times, will similarly not be compatible with a high resistance in series with the pad.
An alternate approach has been to employ a thick oxide device as a parallel discharge path in the input/output buffer circuit. This approach is illustrated in FIG. 2. As shown schematically in FIG. 2, the thick oxide device is a field effect transistor having the gate tied to the input from the pad. The oxide thickness is chosen to provide a threshold voltage for the device such that the device turns on at a desired ESD protection voltage, for example, 30 volts. Thus, when an ESD pulse is applied to the pad, the thick oxide FET will rapidly turn on when the voltage rises above the threshold voltage thereby providing channel conduction and an alternate current discharge path for the ESD pulse. An opposite conductivity type field effect transistor may also be provided which turns on for ESD pulses of the opposite polarity. Also, as indicated in FIG. 2 the thick oxide FET may be combined with a diffusion or polysilicon resistor to provide additional protection against ESD pulses.
As noted above, however, the thin gate oxides of modern CMOS devices are susceptible to relatively low voltage ESD pulses and may break down before the thick oxide FET turns on. Such lower voltage pulses are thus a significant problem. Making the oxide thinner and lowering the threshold voltage thick oxide device will not provide a suitable solution since this then subjects that device to degradation of its gate oxide in response to ESD pulses. Therefore, this device may ultimately fail removing the protection to the circuit and possibly even shorting the circuit. The use of resistors noted above, also have inherent limitations due to the disadvantages of placing a high resistance in series with the buffer circuit and pad.
Accordingly, a need presently exists for an improved integrated circuit design which provides increased resistance to ESD pulses over a wide voltage range without introducing undesirable loads into the input/output circuitry.